Memory testing systems implementing so-called "intelligence per-pin" architecture generally include a plurality of channels. Each channel corresponds and connects to one input of a device under test (DUT). Thus, the number of channels included in a per-pin memory testing system is at least equal to the number of inputs being used during the testing of the DUT. Typically, all channels in an intelligence per-pin testing system operate simultaneously during a test so as to form a parallel pipelined configuration. Per-pin testing systems are desirable because such systems allow for high speed testing and increased flexibility in configuring and generating test data as required for various testing schemes.
Generally, each channel in a per-pin testing system has a memory which stores input data signals, command signals and control signals appropriate for testing the DUT. Each channel also stores a series of address pattern sequences for presenting to the DUT during a test. Unfortunately, a typical channel memory has limited storage capacity which is incapable of storing all address and input data pattern combinations required for presenting to the DUT.
A solution to this problem is to implement an algorithmic address generator which develops address sequences algorithmically. Such a solution would allow for input data signals, command signals and control signals to be applied to the various addresses of the DUT while only one copy of each signal need be stored in channel memory.
In a strictly per-pin type architecture, one algorithmic address generator would be required for each channel. Since the algorithmic address generator generally resides on the same chip as the channel, the generator typically requires minimal central control, thus allowing for high speed address generation. However, having one address generator per each channel results in problems of increased power consumption by the address generators, and increased physical space requirements for packaging of the address generators. Consequently, the capabilities of the address generator may need to be compromised for reducing power consumption, and for reducing the physical size of the address generator for packaging.
Although an alternate approach of implementing a single address generator in common for all channels of the testing system may solve problems of power consumption and space requirements, such a scheme would severely limit address sequencing capabilities of the testing system. Moreover, a testing system having a single algorithmic address generator in common for all channels would require longer control lines for connecting the address generator to the various channels. Longer control lines cause various testing problems during, such as undesirable signal skew to the DUT and increased line delay times.